Very large scale integrated (VLSI) circuit cards are usually the core components in today's highly complex electronic circuitry and/or logic circuitry found in mainframe servers. These circuit cards typically are packaged as multiple chips fabricated on a single card assembly or module, and are inherently referred to as multiple chip modules (MCM). Each chip on a MCM usually
represents a distinct design component, and may have hierarchical components inside them as well.
A variety of design methods are employed in developing each chip, and a chip may be developed concurrently with other chips to speed up the MCM design process. In the end, the finished chips are usually assembled together on the MCM in a pre-determined layout using physical packaging information and the physical orientation of the module.
In a semiconductor chip design, there exist many thousands of wires that connect the various electrical sub-components. These sub-components are the manifestations of a self-imposed hierarchy which is used to partition the design into logical and physical contexts. This aids in the development of the chip because the sub-components can be worked on in parallel to one another, speeding up the design cycle.
The sub-components can take the form of several different entities such as random logic macros (RLM), custom circuit components, memory arrays, bit-stacks, units, super macros, and the like. Because of this hierarchy, a floor plan is usually necessary to arrange the sub-components. Many factors go into developing a floor plan, one of which is its overall effect on chip timing. Careful consideration is also given to congestion to ensure that the chip routing tool is able to successfully route all nets in the chip net list.
When dealing with very complicated and logically densely populated chips, it is often the case that many wires will have less than optimum lengths when traveling from one sub-component to another. This adversely affects the timing by adding resistive and capacitive delay to the wires.
In general the longer the wire, the larger these effects are. These properties, also known as parasitics, also get worse with increasing frequency. One of the goals of chip design is to minimize this resistive-capacitive (RC) delay through the use of chip buffering. By inserting buffers into long wires, essentially breaking them up into shorter wires, the risk of timing degradation due to RC delays is mitigated.